The present invention generally relates to a semiconductor integrated circuit device having a test circuit, and more particularly to a logic LSI device such as a gate array device or a standard cell array device having a test circuit.
There is known a semiconductor integrated circuit device having a plurality of logic cells which are coupled via interconnection lines to thereby provide desired logic circuits. Such a semiconductor integrated circuit device is called a logic LSI device. Examples of the logic LSI device are a gate array device and a standard cell array device.
The recent advance of fabricating logic LSIs provides a drastically increased number of logic cells arranged in one chip. Currently, logic LSIs having tens to hundreds of thousands of logic cells are available. As an increased number of logic cells is used, an increased number of test patters must be provided for testing logic LSIs. It takes a long time to product such test patterns and it is very difficult to determine whether or not desired logic arrangements are realized correctly. From these points of view, there is a strong need to develop semiconductor integrated circuit devices having built-in test circuits capable of easily verifying logic arrangements formed therein.
Japanese Laid-Open Patent Application No. 61-42934 proposes a semiconductor integrated circuit device having a built-in test circuit. Referring to FIG. 1, there is illustrated the outline of the proposed device. A plurality of logic cells 2 are formed on a semiconductor chip 1. A built-in test circuit is composed of row select lines 3, column read lines 4, switch elements 5, a row select ring counter 6, a column select ring counter 7, a data selector 8, a row select clock input terminal 9, a column select clock input terminal 10 and a monitor output terminal 11. The logic cells 2 are interconnected on the basis of a user's design or specification in order to provide desired logic circuits. For the sake of simplicity, such interconnections are not illustrated in FIG. 1.
Output terminals of the logic cells 2 are connected to the column read lines 4 via the switch elements 5. The row select ring counter 6 selects one of the row select lines 3, and the column select ring counter 7 selects one of the column select lines 4, so that the logic cells 2 are selected one by one. The logic state of the output terminal of a selected logic cell 2 is output to the monitor output terminal 11 via the data selector 8. In this way, information about the states of the output terminals of the logic cells 2 is obtained at the monitor output terminal 11 and used for determining whether or not desired logic circuits operate correctly.
The above-mentioned test method is called a matrix proving method or simply an MP method. According to the MP method, it is possible to read out the logic state for each logic cell 2. Thus, it is possible to design logic circuits easily, as compared with a conventional scan path method which uses flip-flops. In addition, the reliability of the MP method is high.
However, the MP method presents the following disadvantages. As has been described previously, logic circuits are based on the user's design or specification. Thus, it is necessary for the users to separately provide for respective test patterns. This is troublesome. Second, in order to set a logic cell to a desired logic state, a test pattern may pass through one or more logic cells. Thus, it is very difficult to set some of the logic cells 2 to desired states. Third, it is impossible to directly write test data into each logic cell 2. In other words, it is impossible to set the input terminal of each logic cell 2 to a desired logic state.